1. Field of the Invention
The present invention relates to a chip package structure, and more particularly, relates to a chip package structure adopting package on package (PoP) technology.
2. Descriptions of the Related Art
Because electronic products have become miniaturized, the internal space in such electronic products has become increasingly smaller. Hence, almost all manufacturers are directing efforts into shrinking the dimensions of the internal elements in the electronic products. The arrangement of chips in smaller space has also become important with regards to integration. According to the package on package (PoP) technology, a plurality of chips are stacked on each other in a single chip package structure, so that a plurality of chips are packaged with the area of the package remaining unchanged. With the PoP technology, the area occupied by the plurality of chips is reduced remarkably only at a cost of a slightly increased thickness of the chip package structure. For this reason, the PoP technology has gradually found wide application in various electronic products.
However, packaging a plurality of chips into a single chip package structure leads to a significant increase of the number of pins in the single chip package structure for connection with other electronic devices, such as printed circuit boards (PCBs). Therefore, in a conventional chip package structure 1 as shown in FIG. 1, a Ball Grid Array (BGA) packaging technology for disposing a plurality of conductive balls 15 on a surface of a substrate 101 is adopted together as a means to increase the number of pins (i.e., conductive balls) for electrical connection.
The conventional chip package structure 1 comprises a single substrate 101, a first chip 111, a second chip 112, a plurality of conductive balls 15, a first wire portion 121, a second wire portion 122, a first adhesive layer 131, a second adhesive layer 132, a plastic layer 141 and an outer plastic layer 144. A first bonding surface 111a of the first chip 111 is partially adhered to a second surface 101b of the substrate 101 by means of the first adhesive layer 131, and is electrically connected to a first surface 101a of the substrate 101 by means of the first wire portion 121 which passes through a via hole 101c of the substrate 101. The plastic layer 141 is formed in the via hole 101c and partially covers the surface 101a of the substrate 101 to protect the first wire portion 121 and to facilitate the packaging process. A second opposite surface 112b of the second chip 112 is adhered to a first opposite surface 111b of the first chip by means of the second adhesive layer 132. A second bonding surface 112a of the second chip 112 is electrically connected to the second surface 101b of the substrate 101 via the second wire portion 122. Finally, the structure is covered by the outer plastic layer 144.
The plurality of conductive balls 15 must be kept off the via hole 101c and the plastic layer 141, so they can only be disposed on the remaining portions of the first surface 101a of the substrate 101. To package a plurality of chips, the substrate 101 is formed with the via hole 101c, so that the first wire portion 121 passes through the via hole 101 to electrically connect the first chip 111 to the substrate 101 without interfering with the second wire portion 122 for electrically connecting the second chip 112 to the substrate 101. Hence, it is impossible for the plurality of conductive balls 15 to be disposed throughout the first surface 101a of the substrate 101, which decreases the allowed number of conductive balls 15.
In summary, the PoP technology used at present for the BGA package fails to meet the demand of increasing the number of pins by effectively increasing the number of conductive balls. In view of this, it is highly desirable in the art to provide a chip package structure capable of packaging a plurality of chips and remarkably increasing the number of conductive balls.